High frequency amplifiers are devices that amplify a high frequency signal and transfer the high frequency signal to a load termination. In high frequency power amplifiers the transfer of the high frequency signal is typically done in successive power amplifier stages, wherein each of the successive power amplifier stages has gradually a larger power capability than a preceding power amplifier stage. The transfer of the high frequency signal through each one of the successive power amplifier stages to the load termination must be carefully designed in order not to attenuate part of the high frequency signal, thereby degrading the high frequency power amplifier performance. Optimization of the transfer of the high frequency signal is achieved by impedance matching. Impedance matching matches a source impedance to a load impedance ensuring maximum transfer of power from the source impedance to the load impedance. Impedance matching is sometimes realized with discrete passive components that offer predetermined high frequency characteristics. Alternatively, integrated passive components are used. Impedance matching is typically performed by impedance matching circuits. An example of impedance matching circuits used in high frequency amplifiers is shown on FIG. 1 of U.S. Pat. No. 7,119,623B2. FIG. 1a of this document shows a similar picture found typically in practical prior-art implementations. FIG. 1a shows a MOS device 10 with a gate G, a source S and a drain D terminal. The MOS device of
FIG. 1a is connected in a common source configuration in which the source terminal S connected to a reference potential is common to the gate terminal G and to the drain terminal D. The gate terminal G and the drain terminal D are respectively an input and an output for the MOS device 10. The reference potential is a ground reference potential GND. A parasitic inductive path 15 is present between the source terminal S and the ground reference potential GND. The parasitic inductive path 15 may be caused by the presence of a physical distance between the actual source terminal S and the effective location of the ground reference potential GND. A parasitic capacitance Cout is present at the output of the MOS device 10 and connected between the drain terminal D and the source terminal S. The parasitic output capacitance Cout has a negative effect on the MOS device 10 performance by adding a frequency-dependent component to the MOS device 10 output impedance. An impedance matching circuit is therefore connected to the drain terminal D of the MOS device 10. The impedance matching circuit shown in FIG. 1a includes a shunt inductive bondwire BW and a shunt capacitor C. The shunt capacitor C is coupled at one side to a reference potential GNDM which may be slightly different than the ground reference potential GND (e.g. at a different location) and at another side to the series bondwire INDS. The shunt capacitor C is usually integrated in a dedicated die DIEA different from a die DIEB in which the MOS device 10 is integrated. The dedicated die DIEA in which the capacitor C is integrated is indicated by the dashed line in FIG. 1a. The shunt inductive bondwire BW is actually a bondwire that connects the capacitor C to the drain terminal D of the MOS device 10. The shunt inductive bondwire BW provides a parallel resonant circuit together with the parasitic output capacitance Cout during operation at the high frequency of interest. The parasitic output capacitance Cout is therefore effectively compensated by the shunt inductive bondwire BW. The shunt inductive bondwire BW is coupled to the ground reference potential GNDM through a large shunt capacitor C to prevent a DC current through the shunt inductive bondwire BW to flow to the reference potential GNDM. The capacitor C is usually coupled to the reference potential GNDM on the dedicated die DIEA either through diffused sinker connections in the case of a high conductive substrate or through vias in the case of a high resistive substrate. One problem of the latter approach is that the semiconductor technology with which the dedicated die DIEA is fabricated has vias electrically connecting the capacitor C to a ground pad underneath the die (e.g. the ground back metallization of the dedicated die DIEA), thereby reducing an effective thickness of the die substrate that may instead be used to build high quality integrated passive components. Furthermore said semiconductor technology integrating the passive components may be mechanical complex and mechanically weak because the vias through which the dedicated die DIEA is connected to the reference potential GNDM need to be electrically connected to a ground pad underneath the dedicated die DIEA. The electrical connection may be obtained by means of solder balls, conductive epoxy or any other suitable means of attaching the dedicated die DIEA to the ground pad. As said another option to connect the capacitor C to the reference potential GNDM is to make use of a high conductive substrate to make a high conductive connection of the capacitor C to the reference potential GNDM. In this case however there are extra losses associated with the high conductivity of the substrate that degrades the quality factor of the integrated passive components. As a consequence the efficiency of the high frequency amplifier may be seriously compromised by the use of any of the above-mentioned options.